š complex_mult.sv
Parameterized complex multiplier for SDR I/Q signal paths ā SDR-LIB
SystemVerilog IEEE 1800-2017SDR Signal ChainFixed-Point DSPCombinational Logic
Architecture ā Complex Multiply and Scale
Stage 1Four signed products
ā
Stage 2Real / imaginary sum
ā
Stage 3Fixed-point scale
ā
Stage 4Overflow & saturation
(are + jĀ·aim) Ā· (bre + jĀ·bim) = (arebre ā aimbim) + j(arebim + aimbre)
Four signed products form the complex result. An arithmetic right shift restores the selected fixed-point scale; each I/Q output is independently checked and optionally clamped.
Parameters
| Parameter | Default | Description |
|---|---|---|
kDataWidth | 16 | Signed input width for every I and Q component. |
kOutWidth | 16 | Signed output width for the real and imaginary results. |
kFracBitsToDrop | 15 | Product fractional bits removed to restore the output Q-format. |
kEnableSaturation | 1'b1 | Clamps each component to the signed output range on overflow. |
Interface
| Signal | Direction | Description |
|---|---|---|
a_re, a_im | Input | First complex signed fixed-point sample. |
b_re, b_im | Input | Second complex signed fixed-point sample. |
y_re, y_im | Output | Scaled complex product. |
overflow_re, overflow_im | Output | Asserted when the corresponding scaled result exceeds the output range. |
saturated_re, saturated_im | Output | Asserted when saturation is enabled and the corresponding result is clamped. |
Implementation source