Polyphase FIR
Parameterized multirate filter engine for SDR signal-processing paths — SDR-LIB
SystemVerilog IEEE 1800-2017SDR Signal ChainFixed-Point DSP1-Cycle Latency
Architecture — Polyphase FIR Data Path
Stage 1Input & phase select
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Stage 2Current + delayed taps
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Stage 3Per-phase MAC
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Stage 4Scale & output
y[n] = Σk=0T−1 hphase,k · x[n−k]
The phase input selects one coefficient bank for each accepted sample. Tap 0 uses the current input sample and the remaining taps use the registered sample history. This makes the block suitable for interpolation, decimation and filter-bank structures.
Parameters
| Parameter | Default | Description |
|---|---|---|
kDataWidth | 16 | Signed input and output sample width. |
kCoeffWidth | 16 | Signed coefficient width. |
kNumPhases | 4 | Independently selectable coefficient phases. |
kTapsPerPhase | 16 | FIR taps in each phase. |
kAccWidth | 48 | Full-precision signed MAC accumulator width. |
kFracBitsToDrop | kCoeffWidth − 1 | LSBs discarded after MAC to restore the target fixed-point scale. |
Port Interface
| Port | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | Processing clock. |
rst_n | Input | 1 | Active-low asynchronous reset. |
s_tvalid | Input | 1 | Input sample valid. |
s_tready | Output | 1 | Module ready to accept an input sample. |
s_tdata | Input | kDataWidth | Signed input sample. |
s_tphase | Input | ⌈log₂(kNumPhases)⌉ | Selected coefficient phase. |
s_tlast | Input | 1 | Input frame marker. |
m_tvalid | Output | 1 | Filtered output valid. |
m_tready | Input | 1 | Downstream ready signal. |
m_tdata | Output | kDataWidth | Signed, scaled FIR result. |
m_tphase | Output | ⌈log₂(kNumPhases)⌉ | Phase associated with the output sample. |
m_tlast | Output | 1 | Forwarded frame marker. |
Source Code — SystemVerilog