Projects
Current FPGA, SDR, and verification platform projects.
SDR_LIB
A fully parameterized, reusable FPGA IP library for Software Defined Radio applications, targeting Xilinx/AMD and Intel/Altera FPGAs (primary target: Zynq-7020). All RTL written in SystemVerilog IEEE 1800-2017 with AXI4-Stream as the standard data transport interface. Covers the complete SDR signal chain — from ADC/DAC interfaces through DDC/DUC, filtering, synchronization, modulation/demodulation, FEC, and packet processing — plus supporting infrastructure (CDC, memory, control plane, debug).
LiteXVerify
Open-source, local-first verification infrastructure for LiteX-based SoC designs. Provides a reproducible workflow for RTL generation, UVM/cocotb testbench creation, simulation, and coverage analysis — all running locally with no cloud dependency. Includes hooks for AI-assisted verification workflows developed with support from Mintaka-AI, our separate engineering automation branch.