Projects

A selection of our FPGA and ASIC design and verification engagements.

Completed
PCIe Gen4 Controller IP

Designed a high-throughput PCIe Gen4 x8 controller in SystemVerilog targeting Xilinx UltraScale+ FPGA. Full UVM testbench with protocol-compliance checks and error-injection coverage.

FPGA PCIe Gen4 UVM SystemVerilog Vivado
Completed
AES-256 Crypto Accelerator

RTL implementation of an AES-256 hardware accelerator for an ASIC security chip. Synthesised with Synopsys Design Compiler; achieved timing closure at 500 MHz in TSMC 28nm.

ASIC AES-256 28nm VHDL Design Compiler
Completed
DDR5 Memory Controller

Full UVM verification environment for a DDR5 memory controller subsystem. Developed comprehensive scoreboard, response checker, and coverage model — achieving 98% functional coverage.

DDR5 UVM Verification SystemVerilog VCS
Ongoing
Ethernet MAC 100G IP

Developing a 100G Ethernet MAC IP core in SystemVerilog for Intel Stratix 10 FPGA. Target: line-rate processing with full IEEE 802.3 compliance verification.

FPGA 100G Ethernet Stratix 10 SystemVerilog Quartus
Completed
RISC-V Core FPGA Prototype

FPGA prototype of a custom 32-bit RISC-V core on Xilinx Zynq-7000 SoC. Included AXI4 interconnect integration, bare-metal BSP, and in-system JTAG debug.

RISC-V Zynq FPGA Proto Verilog AXI4
Ongoing
NoC Interconnect Fabric

Designing a configurable Network-on-Chip interconnect fabric for a multi-core ASIC. Full UVM verification with traffic-model stimulus and latency/throughput analysis.

ASIC NoC UVM SystemVerilog Xcelium

Interested in working with us?

Get in Touch Our Services