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FPGA SDR IP Library

A comprehensive, fully parameterized FPGA IP library for Software Defined Radio applications. Designed for maximum reusability and composability across Xilinx/AMD and Intel/Altera FPGA platforms.

SystemVerilog IEEE 1800-2017
Primary Target: Zynq-7020
AXI4-Stream Interface
150+ RTL Modules
TECHNOLOGY STACK
SDR FPGA SystemVerilog AXI4-Stream Zynq-7020 Vivado Quartus cocotb

Project Overview

SDR_LIB is a completed in-house FPGA IP library at Mintaka LLC, engineered to provide a production-ready foundation for Software Defined Radio systems. The library covers the entire SDR signal chain — from high-speed ADC/DAC interfaces through digital down/up conversion, filtering, synchronization, modulation/demodulation, forward error correction, and packet processing.

Every module is written in SystemVerilog IEEE 1800-2017 and uses AXI4-Stream as the standard data transport interface, enabling seamless composition without glue logic. The library is fully parameterized, supporting various data widths, decimation/interpolation rates, and filter configurations through compile-time parameters.

The primary target platform is the Xilinx Zynq-7020, with the real-time DSP running in the PL (FPGA fabric) while the PS (ARM Cortex-A9 + FreeRTOS) handles register control, AGC setpoints, packet routing, and higher-layer protocols via AXI-Lite and AXI-Stream DMA interfaces.

System Architecture

Complete SDR signal chain from ADC to host and back

RECEIVER CHAIN (RX)
ADC IQ Input └─► DDC Core ──► AGC ──► Carrier Recovery ──► Timing Recovery ──► Packet Detector ──► Host (PS/MCU) │ │ │ [NCO/DDS] [Costas Loop] [Gardner TED] [CIC Decim] [FIR Comp]
TRANSMITTER CHAIN (TX)
Host (PS/MCU) ──► Packet Framer ──► Modulator ──► DUC Core ──► DAC IQ Output │ [CIC Interp] [FIR Interp] [NCO/DDS]
ZYNQ-7020 PARTITION
Domain Responsibility
PL (FPGA) Real-time DSP at ADC/DAC sample rate — this IP library
PS (ARM) Register control, AGC setpoints, packet routing, higher-layer protocols (FreeRTOS)
AXI-Lite PS writes frequency tuning word, gain, decimation rate to PL registers
AXI-Stream DMA IQ data transfer between PL and PS DDR

Module Groups

22 functional categories covering the complete SDR IP stack

Packages

Shared types, parameters, AXI-Stream interface definitions

Fixed-Point

Resize, round, saturate, clip detect, gain, shift operations

Complex Math

Add, multiply, conjugate, abs², scale, rotate, mix

NCO / DDS

Phase accumulator, LUT and CORDIC-based DDS, complex NCO

CORDIC

sin/cos, atan2, vectoring, rotation, polar↔cartesian

Filters

FIR, CIC, halfband, polyphase, boxcar — decimate & interpolate

DDC

Digital Down Converter: mixer → CIC → FIR → baseband IQ

DUC

Digital Up Converter: baseband IQ → FIR → CIC → mixer

Sync / AGC

Power estimator, RSSI, AGC loop, gain apply, saturator

Sync / Carrier

Costas loop, complex PLL, freq/phase error estimators

Sync / Timing

Gardner TED, Mueller-Müller, symbol timing, fractional delay

Sync / Frame

Preamble correlator, sync word detector, frame aligner

Modulation

BPSK, QPSK, OQPSK, OOK, FSK, GFSK, GMSK, QAM16, QAM64

Demodulation

All demods + LLR/soft-decision output for FEC

FFT

Radix-2, streaming FFT/IFFT, windowing, spectrum analysis

Channelizer

Polyphase filter bank, FFT channelizer, channel select

OFDM

CP insert/remove, FFT RX/TX, pilots, channel estimation

FEC

CRC, scrambler, conv/Viterbi, Reed-Solomon, LDPC, Polar

Packet

Framer, deframer, header parser, CRC, stream packetizer

Stream

FIFO, register slice, width converter, mux, demux

CDC

Async FIFO, pulse/level/bus sync, reset synchronizer

Memory

Single/dual/true-dual-port RAM, ROM, delay line, buffers

Interfaces

ADC/DAC capture, IQ formatter, JESD204, LVDS, SPI RF

Control

Register bank, AXI-Lite/Wishbone slave, SPI/UART/I2C

Debug

ILA wrapper, stream monitor, overflow/underflow, IQ capture

Completed Development Scope

Implemented scope from foundation blocks to advanced DSP modules

Stage 1 — Foundation

Core building blocks and infrastructure primitives

fxp_resize fxp_saturate complex_add complex_mult complex_abs2 stream_fifo async_fifo nco_dds fir_direct cic_decimator cic_interpolator
Stage 2 — SDR Receiver Chain

Complete receive path from ADC to decoded packets

ddc_core power_estimator agc_loop preamble_correlator packet_detector crc_checker bpsk_demod qpsk_demod
Stage 3 — SDR Transmitter Chain

Complete transmit path from packets to DAC

duc_core bpsk_mod qpsk_mod interpolation_fir packet_framer scrambler dac_sample_output
Stage 4 — Advanced DSP

Synchronization loops, spectrum processing, and advanced modulation

costas_loop gardner_timing_recovery fft_streaming polyphase_channelizer ofdm_rx ofdm_tx viterbi_decoder

Coding Standards

Aspect Standard
Language SystemVerilog IEEE 1800-2017
Organization One module per file, filename = module name
Parameters kCamelCase prefix (e.g., kDataWidth)
Ports snake_case; AXI-Stream slave = s_*, master = m_*
Reset Active-low asynchronous (rst_n), synchronous release
Types Imported from sdr_types_pkg; use logic not wire/reg
PACKAGE IMPORT
// In any RTL module, import shared types with: import sdr_types_pkg::*; import sdr_params_pkg::*;
FILELIST USAGE
# Vivado TCL read_sv -filelist [file normalize sdr_lib.f] # ModelSim / Questa vlog -sv -f sdr_lib.f # VCS vcs -sv -f sdr_lib.f # Icarus Verilog iverilog -f sdr_lib.f

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