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SDR-LIB: FPGA IP Library

A working, fully parameterized FPGA IP library of synthesizable, configurable blocks for Software Defined Radio systems. Developed by Mintaka as a full FPGA design and verification project, it is designed for reuse and composition across Xilinx/AMD and Intel/Altera FPGA platforms.

SystemVerilog IEEE 1800-2017
Orion FPGA Platforms
AXI4-Stream Interface
210+ Synthesizable IP Modules
TECHNOLOGY STACK
SDR FPGA SystemVerilog AXI4-Stream Orion Platform Vivado Quartus cocotb

Overview

SDR-LIB is Mintaka's in-house FPGA IP library, actively used across our FPGA, SDR and SatCom engineering services. It provides a production-ready foundation for Software Defined Radio systems. The library covers the entire SDR signal chain — from high-speed ADC/DAC interfaces through digital down/up conversion, filtering, synchronization, modulation/demodulation, forward error correction, and packet processing.

It contains 210+ synthesizable RTL/IP modules organized into 25 functional groups: foundational packages and fixed-point math; DSP, synchronization and modulation chains; OFDM and FEC; streaming, CDC, memory, interfaces, control and debug infrastructure.

Every module is written in SystemVerilog IEEE 1800-2017 and uses AXI4-Stream as the standard data transport interface, enabling seamless composition without glue logic. The library is fully parameterized, supporting various data widths, decimation/interpolation rates, and filter configurations through compile-time parameters.

Copernicus AI Copilot helps engineers configure and combine these ready-to-synthesize blocks into SDR system architectures. The engineer remains in control of the architecture, requirements and implementation decisions.

SDR-LIB works with FPGA hardware platforms in the Orion Signal Research Platform, where its real-time processing blocks are configured, integrated and evaluated as part of complete SDR communication systems.

System Architecture

Complete SDR signal chain from ADC to host and back

RECEIVER CHAIN (RX)
ADC IQ Input └─► DDC Core ──► AGC ──► Carrier Recovery ──► Timing Recovery ──► Packet Detector ──► Host (PS/MCU) │ │ │ [NCO/DDS] [Costas Loop] [Gardner TED] [CIC Decim] [FIR Comp]
TRANSMITTER CHAIN (TX)
Host (PS/MCU) ──► Packet Framer ──► Modulator ──► DUC Core ──► DAC IQ Output │ [CIC Interp] [FIR Interp] [NCO/DDS]
FPGA PLATFORM PARTITION
Domain Responsibility
FPGA Fabric Real-time SDR processing using SDR-LIB's synthesizable IP blocks
Host / Control Configuration, orchestration, data handling and higher-layer system functions
Control Plane Configuration of frequency, gain, rates and other SDR-LIB block parameters
Data Plane Streaming IQ and packet data between FPGA processing and the system host

Module Groups

25 functional IP groups covering the complete SDR signal-processing and system-infrastructure stack

Packages

Shared types, parameters, AXI-Stream interface definitions

Fixed-Point

Resize, round, saturate, clip detect, gain, shift operations

View example: fxp_resize.sv
Complex Math

Add, multiply, conjugate, abs², scale, rotate, mix

View example: complex_mult.sv
NCO / DDS

Phase accumulator, LUT and CORDIC-based DDS, complex NCO

CORDIC

sin/cos, atan2, vectoring, rotation, polar↔cartesian

Filters

FIR, CIC, halfband, polyphase, boxcar — decimate & interpolate

View example: fir_polyphase.sv
DDC

Digital Down Converter: mixer → CIC → FIR → baseband IQ

DUC

Digital Up Converter: baseband IQ → FIR → CIC → mixer

Sync / AGC

Power estimator, RSSI, AGC loop, gain apply, saturator

Sync / Carrier

Costas loop, complex PLL, freq/phase error estimators

Sync / Timing

Gardner TED, Mueller-Müller, symbol timing, fractional delay

Sync / Frame

Preamble correlator, sync word detector, frame aligner

Modulation

BPSK, QPSK, OQPSK, OOK, FSK, GFSK, GMSK, QAM16, QAM64

Demodulation

All demods + LLR/soft-decision output for FEC

FFT

Radix-2, streaming FFT/IFFT, windowing, spectrum analysis

Channelizer

Polyphase filter bank, FFT channelizer, channel select

OFDM

CP insert/remove, FFT RX/TX, pilots, channel estimation

FEC

CRC, scrambler, conv/Viterbi, Reed-Solomon, LDPC, Polar

Packet

Framer, deframer, header parser, CRC, stream packetizer

Stream

FIFO, register slice, width converter, mux, demux

CDC

Async FIFO, pulse/level/bus sync, reset synchronizer

Memory

Single/dual/true-dual-port RAM, ROM, delay line, buffers

Interfaces

ADC/DAC capture, IQ formatter, JESD204, LVDS, SPI RF

Control

Register bank, AXI-Lite/Wishbone slave, SPI/UART/I2C

Debug

ILA wrapper, stream monitor, overflow/underflow, IQ capture

Coding Standards

Aspect Standard
Language SystemVerilog IEEE 1800-2017
Organization One module per file, filename = module name
Parameters kCamelCase prefix (e.g., kDataWidth)
Ports snake_case; AXI-Stream slave = s_*, master = m_*
Reset Active-low asynchronous (rst_n), synchronous release
Types Imported from sdr_types_pkg; use logic not wire/reg
PACKAGE IMPORT
// In any RTL module, import shared types with: import sdr_types_pkg::*; import sdr_params_pkg::*;
FILELIST USAGE
# Vivado TCL read_sv -filelist [file normalize sdr_lib.f] # ModelSim / Questa vlog -sv -f sdr_lib.f # VCS vcs -sv -f sdr_lib.f # Icarus Verilog iverilog -f sdr_lib.f

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